1. Field of the Invention
The present invention generally relates to liquid-crystal displays, and more particularly to a controller for controlling drivers which drive a liquid-crystal display panel so that display timings at which image data is displayed on the panel are controlled.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional liquid-crystal display device of an XGA type (1024xc3x97768 dots). The device includes a liquid-crystal display panel 10 of an active matrix type, a data driver 11, a gate driver 12 and a liquid-crystal display timing controller 13. The data driver 11 drives a data bus (signal lines) formed on the liquid-crystal display panel 10. The gate driver 12 drives a gate bus (scanning lines) formed on the liquid-crystal display panel 10.
The timing controller 13 receives, from an image data supply source (not shown), a vertical synchronizing signal VSYNC, a horizontal synchronizing signal HSYNC, a clock CLK, a data enable signal ENAB and image data DATA, and controls, based on the vertical synchronizing signal VSYNC and the horizontal synchronizing signal HSYNC, display timings at which the image data DATA is displayed on the panel 10.
The timing controller 13 supplies the data driver 11 with a data driver clock D-CLK, a data driver start pulse D-SP, a latch pulse LP and image data DATA, and supplies the gate driver 12 with a gate driver clock G-CLK and a gate driver start pulse G-SP.
FIG. 2 is a timing chart showing a drive timing in the horizontal direction of the conventional liquid-crystal display device shown in FIG. 10. Part (A) of FIG. 11 shows the horizontal synchronizing signal HSYNC, part (B) shows the clock CLK, part (C) shows the image data DATA, and part (D) shows the data enable signal ENAB. Further, a symbol Th denotes a horizontal cycle period, Thp denotes a horizontal blanking period, Thd denotes a display valid period, Thb denotes a back porch of the display valid period Thd, and Thf denotes a front porch of the display valid period Thd.
FIG. 3 is a drive timing in the vertical direction of the conventional liquid-crystal display device shown in FIG. 1. Part (A) of FIG. 3 shows the vertical synchronizing signal VSYNC, part (B) shows the horizontal synchronizing signal HSYNC, part (C) shows the image data DATA, and part (D) shows the data enable signal ENAB. Further, a symbol Tv denotes a vertical cycle period, Tvp denotes a vertical blanking period, Tvd denotes a display valid period, Tvb denotes a back porch of the display valid period Tvd, and Tvf is a front porch of the display valid period Tvd.
FIG. 4 shows a relationship between a data display area 15 and a blank area 16 during one vertical cycle period of the conventional liquid-crystal display device shown in FIG. 1. The data display area 15 includes pixels arranged in a matrix formation. The blank area 16 does not have pixels. The horizontal length of the blank area 16 amounts to 1184 clocks, and the vertical length thereof is equal to 806 lines. The horizontal length of the data display area 15 amounts to 1024 clocks, and the vertical length thereof is equal to 768 lines.
However, the above-mentioned prior art has the following disadvantages.
The timing controller 13 has the fixed values of the back porches Thb and Tvb and the fixed values of the front porches Thf and Tvf. The back porches Thb and Tvb and the front porches Thf and Tvf define the display timing (display period) of the liquid-crystal panel 10. In other words, the timings of the display valid periods Thd and Tvd are fixed. The timing controller 13 controls the data driver 11 and the gate driver 12 by using the fixed values of the back porches Thb and Tvb and front porches Thf and Tvf.
As shown in FIG. 4, if the fixed values of the back porches Thb and Tvb exactly indicate the starting pixel of the data display area 15 located in the first line and scanned by the first clock of the 1024 clocks, the image data can correctly be displayed on the data display area 15 during the data valid periods Thd and Tvd in synchronism with the data enable signal ENAB.
The values of the back porches Thb and Tvb and those of the front porches Thf and Tvf depend on the timing specification of an electronic device such as a personal computer to which the liquid-crystal display device is provided. For example, the timing specification of the electronic device is first determined, and the fixed values of the back porches Thb and Tvb and those of the front porches Thf and Tvf are then selected so as to meet the specification. Alternatively, the timing specification of the electronic device is determined so as to conform with the fixed values of the back porches Thb and Tvb and those of the front porches Thf and Tvf.
If the fixed values of the back porches Thb and Tvb and those of the front porches Thf and Tvf do not match the timing specification of the electronic device, the image data cannot be correctly displayed on the data display area 15. For example, the image data is offset on the data display area 15 in the vertical and/or horizontal direction thereof and some image is lost.
Hence, the timing controller 13 cannot be applied to various timing specifications of the electronic devices to which the liquid-crystal display device is provided, but can be applied to the specific timing specification only. In practice, the timing controllers 13 having the different timing specifications are designed so as to meet the respective timing specifications of electronic devices to which the liquid-crystal display devices are provided. Usually, it takes a long time (for example, one month) to design the timing controller 13 and ship samples thereof, and it takes a further long time (for example, two months) to go into quantity production. Hence, the above-mentioned disadvantages of the prior art make it difficult to rapidly develop and manufacture electronic devices having the respective timing specifications.
It is a general object of the present invention to provide a controller for a liquid-crystal display panel in which the above-mentioned disadvantages are eliminated.
A more specific object of the present invention is to provide a controller for a liquid-crystal display panel which can be applied to various timing specifications of electronic devices to which the liquid-crystal display panel is provided.
The above objects of the present invention are achieved by a timing controller for a liquid-crystal display panel comprising: a data enable signal detection circuit (20) which detects a data enable signal applied to the timing controller; and a timing generating circuit (32) which controls a display timing of image data to be displayed on the liquid-crystal display panel on the basis of the data enable signal detected by the data enable signal detection circuit.
The above timing controller may be configured so that the timing generating circuit comprises a first circuit (FIG. 15C) which generates, from the data enable signal, a first start pulse (D-ST) which starts driving each data line of the liquid-crystal display panel, and a second circuit (FIG. 15F) which generates, from the data enable signal, a second start pulse (G-SP) which starts driving scanning lines of the liquid-crystal display panel.
The above timing controller may be configured so that the timing generating circuit comprises a circuit part (FIG. 15F) which detects a beginning of each frame on the basis of the data enable signal.
The timing controller may further comprise: a synchronizing signal detection circuit (22, 23, 24) which detects vertical and horizontal synchronizing signals; and a pseudo-data-enable signal generating circuit (25) which generates a pseudo-data-enable signal when the synchronization signal detection circuit detects the vertical and horizontal synchronizing signals while the data enable signal detection circuit does not detect the data enable signal, wherein the timing generating circuit controls the display timing of image data on the basis of the pseudo-data-enable signal.
The timing controller may further comprise: a synchronizing signal detection circuit (22, 23, 24) which detects vertical and horizontal synchronizing signals; and a protection circuit (27) which generates a pseudo-data-enable signal when the data enable signal and the vertical and horizontal synchronizing signals are not detected, wherein the timing generating circuit controls the display timing of image data on the basis of the pseudo-data-enable signal.
Another object of the present invention is to provide a method of controlling a display timing for a liquid-crystal display panel, the method comprising the steps of: (a) detecting a data enable signal applied together with image data (step ST2); and (b) controlling the display timing of the image data to be displayed on the liquid-crystal display panel on the basis of the data enable signal detected by the step (a) (step ST3).
A further object of the present invention is to provide a liquid-crystal display device equipped with the above timing controller.
This object of the present invention is achieved by a liquid-crystal display device comprising: a liquid-crystal display panel (10) having signal lines and scanning lines; a data driver (11) which drives the signal lines; a gate driver (12) which drives the scanning lines; and a timing controller (FIG. 5) controlling a display timing of image data to be displayed on the liquid-crystal display panel. The timing controller comprises: a data enable signal detection circuit (20) which detects a data enable signal applied to the timing controller; and a timing generating circuit (32) which controls the display timing on the basis of the data enable signal detected by the data enable signal detection circuit.
The above liquid-crystal display device may be configured so that the timing generating circuit comprises a first circuit (FIG. 15C) which generates, from the data enable signal, a first start pulse (D-ST) which starts driving each of the data lines, and a second circuit (FIG. 15F) which generates, from the data enable signal, a second start pulse (G-SP) which starts driving the scanning lines.
The liquid-crystal display device may be configured so that the timing generating circuit comprises a circuit part (FIG. 15F) which detects a beginning of each frame on the basis of the data enable signal.
The liquid-crystal display device may further comprise: a synchronizing signal detection circuit (22, 23, 24) which detects vertical and horizontal synchronizing signals; and a pseudo-data-enable signal generating circuit (25) which generates a pseudo-data-enable signal when the synchronization signal detection circuit detects the vertical and horizontal synchronizing signals while the data enable signal detection circuit does not detect the data enable signal, wherein the timing generating circuit controls the display timing of image data on the basis of the pseudo-data-enable signal.
The liquid-crystal display device may further comprise: a synchronizing signal detection circuit (22, 23, 24) which detects vertical and horizontal synchronizing signals; and a protection circuit (27) which generates a pseudo-data-enable signal when the data enable signal and the vertical and horizontal synchronizing signals are not detected, wherein the timing generating circuit controls the display timing of image data on the basis of the pseudo-data-enable signal.
The liquid-crystal display device may further comprise: a synchronizing signal detection circuit (22, 23, 24) which detects vertical and horizontal synchronizing signals; a pseudo-data-enable signal generating circuit (25) which generates a first pseudo-data-enable signal when the synchronization signal detection circuit detects the vertical and horizontal synchronizing signals while the data enable signal detection circuit does not detect the data enable signal; and a protection circuit (27) which generates a second pseudo-data-enable signal when the data enable signal and the vertical and horizontal synchronizing signals are not detected, wherein the timing generating circuit controls the display timing of image data on the basis of any of the data enable signal, the first pseudo-data-enable signal and the second pseudo-data-enable signal.